A simple matrix type ferroelectric memory device using only ferroelectric capacitors instead of cell transistors has a very simple structure and enables a higher degree of integration. Therefore, development of such a memory device has been expected.
Japanese Patent Application Laid-open No. 9-116107 discloses technology relating to a simple matrix type ferroelectric memory device and an operation method therefor.
A method of writing and reading data disclosed in Japanese Patent Application Laid-open No. 9-116107 is described below. FIG. 9 is a view showing a memory cell array of a ferroelectric memory device.
The method of writing data is described below. FIG. 10 is a timing chart in the case of writing data “1” into a ferroelectric capacitor Cm,N and writing data “0” into Cm,N+1. In the technology according to Japanese Patent Application Laid-open No. 9-116107, the data “1” is written into a memory cell by applying a voltage in a direction so that the potential of a selected sub-bit line is higher than the potential of a selected word line. The data “0” is written into the memory cell by applying a voltage in a direction so that the potential of the selected sub-bit line is lower than the potential of the selected word line.
Main bit lines MBLN and MBLN+1 are set to a ground voltage (0 V) at a time t1. At the same time, a selection gate line SL is set to 5 V from 0 V, a selected word line WLm is set to a power supply voltage VCC (3.3 V), and all non-selected word lines WL1 to WLm are set to the ground voltage (0 V) This causes the contents of the ferroelectric capacitors Cm,N and Cm,N+1 to be erased (data “0” is written).
At a time t2, the selection gate line SL and the selected word line WLm are set to the ground voltage (0 V), the main bit line MBLN is set to the power supply voltage VCC (3.3 V), and the main bit line MBLN+1 is set to (⅓) VCC (1.1 V).
At a time t3, the selection gate line SL is set to 5 V, the selected word line WLm is set to the ground voltage (0 V), and the non-selected word lines WL1 to WLM are set to (⅔) VCC (2.2 V). This causes the data “1” to be written into the ferroelectric capacitor Cm,N.
At a time t4, the main bit lines MBLN and MBLN+1 are set to (⅓) VCC (1.1 V), and the selection gate line SL and the word lines WL1 to WLM are set to the ground voltage (0 V), whereby the write operation is completed.
The method of reading data is described below. FIG. 11 is a timing chart in the case of reading the data “1” stored in the memory cell Cm,N and reading the data “0” stored in the memory cell Cm,N+1, and rewriting the data “1” into the memory cell Cm,N and rewriting the data “0” into Cm,N+1.
At the time t1, a precharge signal φPC is set to the power supply voltage VCC (3.3 V), and a column select signal φ is set to 5 V. This causes the main bit lines MBLN and MBLN+1 to be precharged to a precharge voltage VPC (0 V) before time t2. The main bit lines MBLN and MBLN+1 are respectively connected to nodes VN and VN+1 of sense amplifiers.
At the time t2, the precharge signal φPC is dropped to 0 V, thereby causing the main bit lines MBLN and MBLN+1 to be in a floating state. The selection gate line SL is set to 5 V from 0 V, and the selected word line WLm is set to the power supply voltage VCC (3.3 V) from 0 V. This causes the ferroelectric capacitors Cm,N and Cm,N+1 to be in a polarization state in which the data “0” is written.
At the time t3, the selection gate line SL and the selected word line WLm are set to 0 V. At the time t4, a sense enable signal φSE is set to the power supply voltage VCC (3.3 V). This causes sense amplifiers SAN and SAN+1 to be activated. As a result, the data “1” is latched by the sense amplifier SAN before a time t5, whereby the potential of the main bit line MBLN is set to the power supply voltage VCC (3.3 V). The data “0” is latched by the sense amplifier SAN+1, whereby the potential of the main bit line MBLN+1 is set to the ground voltage (0 V) The read operation is performed in this manner.
Since steps after the time t5 are rewriting steps, description thereof is omitted.